Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation

STATIC CMOS ICs WITH VERY LOW GLITCH POWER DISSIPATION NIHAR R. MAHAPATRA SRIRAM V. GARIMELLA ALWIN TAREEN [email protected] [email protected] [email protected] Department of Computer Science & Engineering VLSI Systems Group Department of Electrical Engineering State University of New York at Buffalo Seagate Technology, Inc. State University of New York at Buffalo Buffalo, NY 14260, USA Scotts Valley, CA 95066, USA Buffalo, NY 14260, USA Abstract This paper presents a new framework called gate triggering for systematically minimizing glitch power dissipation in static CMOS ICs. It is based on the idea that glitches can be effectively minimized by triggering logic evaluation at a gate only when all of its inputs have stabilized. For this purpose, to every potentially glitchy gate (or a suitable subset of such gates) is added a small amount of control logic, which, when enabled, triggers logic evaluation at the gate. A clocked delay chain is employed to generate enable signals at the proper times for all gates to be triggered. We present six specific techniques based on gate triggering that differ in the type of control logic and the way it is used to control a gate. These techniques have varying effectiveness and area and timing overheads, which we analyze in detail. Application of these techniques to test circuits yields promising results.